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uniform sector dual and quad serial flash GD25Q128b 1 GD25Q128 datasheet 4 3 - 1 r ev.1. 1 uniform sector dual and quad serial flash GD25Q128b 1 GD25Q128 datasheet free datasheet http://
2 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 2 contents 1. features ................................................................................................ ..................................................... 4 2. general description ............................................................................................................................. 5 3. memory organizat ion ........................................................................................................................... 7 4. device operation ................................................................................................ ..................................... 8 5. data protection ................................................................................................ ...................................... 9 6. status regis ter ................................................................................................ ..................................... 11 7. commands description ....................................................................................................................... 13 t able of id d efinitions : .................................................................................................................................................... 15 7.1. w rite e nable (wren) (06h) ................................................................................................................................ 16 7.2. w rite d isable (wrdi) (04h) ................................................................................................................................ 16 7.3. r ead s tatus r egister (rdsr) (05h or 35h) .......................................................................................................... 16 7.4. w rite s tatus r egister (wrsr) (01h) ................................................................................................................... 17 7.5. r ead d ata b ytes (read) (03h) ............................................................................................................................. 17 7.6. r ead d ata b ytes a t h igher s peed (f ast r ead ) (0bh) ............................................................................................. 18 7.7. d ual o utput f ast r ead (3bh) .............................................................................................................................. 18 7.8. q uad o utput f ast r ead (6b h) ............................................................................................................................. 19 7.9. d ual i/o f ast r ead (bbh) .................................................................................................................................... 19 7.10. q uad i/o f ast r ead (ebh) ................................................................................................................................... 21 7.11. q uad i/o w ord f ast r ead (e7h) ......................................................................................................................... 22 7.12. p age p rogram (pp) (02h) .................................................................................................................................... 23 7.13. q uad p age p rogram (32h) .................................................................................................................................. 24 7.14. s ector e rase (se) (20h) ....................................................................................................................................... 25 7.15. 32kb b lock e rase (be) (52h) ............................................................................................................................... 25 7.16. 64 kb b lock e rase (be) (d8h) ............................................................................................................................... 26 7.17. c hip e rase (ce) (60/c7h) ..................................................................................................................................... 26 7.18. d eep p ower -d own (dp) (b9h) ............................................................................................................................. 27 7.19. r elease from d eep p ower -d own a nd r ead d evice id (rdi) (abh) ......................................................................... 27 7.2 0. r ead m anufacture id/ d evice id (rems) (90h) ................................................................................................... 28 7.21. r ead m anufacture id/ d evice id d ual i/o (92h) ................................................................................................ . 29 7.22. r ead m anufacture id/ d evice id q uad i/o (94h) ................................................................................................ . 29 7.23. r ead i dentification (rdid) (9fh) ......................................................................................................................... 30 7.24. c ontinuous r ead m ode r eset (crmr) (ffh) ........................................................................................................ 31 7.25. p rogram /e rase s uspen d (pes) (75h) ................................................................................................................... 31 7.26. p rogram /e rase r esume (per) (7ah) ................................................................................................................... 32 7.27. e rase s ecurity r egisters (44h) ............................................................................................................................ 32 7.28. p rogram s ecurity r egisters (42h) ....................................................................................................................... 33 7.29. r ead s ecurity r egisters (48h) ............................................................................................................................. 34 8. electrica l characteristics ........................................................................................................... 35 4 5 7 8 9 11 13 15 16 16 16 17 17 18 18 19 19 21 22 23 24 25 25 26 26 27 27 28 29 29 30 31 31 32 32 33 34 35 free datasheet http://
3 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 3 8.1. power - on timing ........................................................................................................................................... 35 8.2. initial delivery state ..................................................................................................................................... 35 8.3. data retention and endurance ................................................................................................................. 35 8.4. latch up characteristics ............................................................................................................................. 35 8.5. absolute maximum ratings ........................................................................................................................ 36 8.6. capacitance measurement conditions .................................................................................................... 36 8.7. dc characteristic .......................................................................................................................................... 37 8.8. ac characteristics ......................................................................................................................................... 38 9. ordering information ........................................................................................................................ 40 10. package information ...................................................................................................................... 41 10.1. p ackage sop16 300mil ...................................................................................................................................... 41 10.2. p ackage wson8 (8*6 mm ) ................................................................................................................................... 42 10.3. p ackage tfbga - 24ball (6*4 ball array ) ............................................................................................................ 43 43 42 41 41 40 38 37 36 36 35 35 35 3 5 free datasheet http://
4 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 4 1. f eatures ? 128 m- bit serial flash ? program/erase s peed - 16348 k- byte - page program time: 0. 4 ms typical - 256 bytes per programmable page - sector erase time: 100m s typical - block erase time: 0. 2 /0. 4 s typical ? standard, dual, quad spi - chip erase time: 60s typical - standard spi: sclk, cs#, si, so, wp#, hold# - dual spi: sclk, cs#, io0, io1, wp#, hold# ? flexible architecture - quad spi: sclk, cs#, io0, io1, io2, io3 - sector of 4k - byte -b lock of 32/64 k- byte ? high speed clock frequency ? low power c onsumption - 104 mhz for fast read with 3 0pf load - 20 ma maximum active current - dual i/o data transfer up to 208mbits/s -5 ua maximum power down current - quad i/o data transfer up to 416mbits/s ? advanced security features (1) - 16 - bit customer id ? software/hardware write protection - 4*256 - byte security registers with otp lock -w rite protect all/portion of memory via software - enable/disable protection with wp# pin ? single power supply v oltage - top or bottom, sector or block selection - full voltage range:2.7~3.6v ? minimum 100,000 program/erase c ycles ? package information - sop16 (300mil) ? typical 10 years data retention - wson8 (8*6mm) - tfbga24 (6*4 ball array) free datasheet http://
5 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 5 2. g eneral d escription the gd25 q 128 b ( 128 m- bit) s erial flash support s the standard seri al peripheral interface (spi), and supports the dual/quad spi: serial clock, chip select, serial data i/o0 (si), i/o1 (so), i/o2 ( wp#), and i/o3 (hold# ) . the dual i/o data is transfer red with spe ed of 208 mbits/s and the quad i/o & quad output data is transfer red with speed of 4 16 mbits/s. c onnection diagram p in description pin name i/o description cs # i chip select input so (io1) i/o data output (data input output 1) wp # (io2) i/o write protect input (data input output 2) vss ground s i (io0) i/o data input (data input output 0) sclk i serial clock input hold # (io3) i/o hold input (data input output 3) vcc power supply nc no connect cs # so wp # vss top view vcc hold # sclk si 16 - lead sop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc nc nc nc nc nc nc nc cs # so wp # vss top view vcc hold # sclk si 8 C lead wson 1 2 3 4 5 6 7 8 vcc wp # hold # vss si so cs # sclk nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc a b c d e f 4 3 2 1 24 - ball tfbga top view free datasheet http://
6 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 6 b lock diagram spi command & control logic high voltage generators page address latch / counter status register write control logic byte address latch / counter column decode and 256 - byte page buffer write protect logic and row decode flash memory cs # sclk si( io 0) so( io 1) hold #( io 3) wp #( io 2) free datasheet http://
7 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 7 3. memory organization gd25q 128 b each device has each block has eac h sector has each page has 16 m 64/32 k 4k 256 bytes 64 k 256/128 16 - pages 4096 16 /8 - - sectors 256 / 512 - - - blocks uniform block sector architecture g d25q 128 b 64k bytes block sector architecture block sector address range 255 4095 f ff000 h f fffff h 408 0 f f0000 h f f0fff h 254 40 79 f ef000 h f effff h 40 64 f e0000 h f e0fff h 2 47 02f000 h 02ffff h 32 020000 h 02 0 fff h 1 31 01f000 h 01ffff h 16 010000 h 010fff h 0 15 00 f000 h 00 ffff h 0 00 0000 h 00 0fff h free datasheet http://
8 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 8 4. device operation spi mode standard spi the gd25 q 128 b feature s a serial peripheral interface on 4 signals bus : serial clock ( s clk), chip select (cs#), serial data input ( s i) and serial data output ( s o). both spi bus mode 0 and 3 are supported . input data is latched on the rising edge of sclk and data shifts out on the falling edge of sclk . dual spi the gd25 q 128 b supports dual spi operation when using the dual output fast read and dual i/o fast read (3b h and bb h) commands. these commands allow data to be transferred to or from the device at two times the rate of the standard spi. w hen using the dual spi command the si and so pins become bidirectional i/o pins: io0 and io 1. quad spi the gd25 q 128 b supports quad spi operation when us ing the quad output fast read , quad i/o fast read , quad i/o word fast read (6b h, ebh, e7h) commands. these commands allow data to be transferred to or from the device at four times the rate of the standard spi. w hen using the quad spi command the si and so pins become bidirectional i/o pins: io0 and io1, and wp# and hold# pins become io2 and io3. quad spi commands require the non - volatile quad enable bit (qe) in status register to be s et. hold the hold# signal goes low to stop any serial communications with the device, but doesn t stop the operation of write status register, programming, or erasing in progress. the operation of hold, need cs# keep low, and starts on falling edge of the hold# signal, with sclk signal being low (if sclk is not being low, hold operation will not start until sclk being low) . th e hold condition ends on rising edge of hold# signal with sclk being low (if sclk is not being low, hold operation will not end until sclk being low). the so is high impedance, both si and sclk don t care during the hold operation, i f cs# drive s high during hold operation, it will reset the internal logic of the device. to re - start communication with chip, the hold# must be at high an d then cs# must be at low. figure 1 . hold condition hold hold cs # sclk hold # free datasheet http://
9 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 9 5. d ata protection the gd25 q 128 b provide the following data protection methods: ? w rite enable (wren) command: the wren command is set the write enable latch bit (wel). the wel bit will return to reset by the following situation: - power -up - write disable (wrdi) - write status register (wrsr) - page program (pp) - sector erase (se) / block erase (be) / chip erase (ce) ? s oftware protection mode: the block protect (bp4, bp3, bp2, bp1, bp0) bits define the section of the memory array that can be read but not change. ? hardware protection mode: wp# going low to protected the bp0~bp 4 bits and srp 0~1 bit s. ? deep power -d own mode: in deep power -d own m ode, all commands are ignored except the release from deep power -d own mode command. table1. 0 g d25q128 b protected area size (cmp=0) status register content memory content b p4 bp3 bp2 bp1 bp0 blocks addresses density portion x x 0 0 0 none none none none 0 0 0 0 1 252 to 255 fc0000h - ffffffh 256kb up per 1/64 0 0 0 1 0 248 to 255 f80000h - ffffffh 512kb upper 1/32 0 0 0 1 1 240 to 255 f00000h - ffffffh 1mb upper 1/16 0 0 1 0 0 224 to 255 e00000h - ffffffh 2mb upper 1/8 0 0 1 0 1 192 to 255 c00000h - ffffffh 4mb upper 1/4 0 0 1 1 0 128 to 255 8 00000h - ffffffh 8mb upper 1/2 0 1 0 0 1 0 to 3 000000h - 03ffffh 256kb lower 1/64 0 1 0 1 0 0 to 7 000000h - 07ffffh 512kb lower 1/32 0 1 0 1 1 0 to 15 000000h - 0fffffh 1mb lower 1/16 0 1 1 0 0 0 to 31 000000h - 1fffffh 2mb lower 1/8 0 1 1 0 1 0 to 63 000000h - 3fffffh 4mb lower 1/4 0 1 1 1 0 0 to 127 000000h - 7fffffh 8mb lower 1/2 x x 1 1 1 0 to 255 000000h - ffffffh 16mb all 1 0 0 0 1 255 f ff000h -f fffffh 4kb top block 1 0 0 1 0 255 f fe000h -f fffffh 8kb top block 1 0 0 1 1 255 f fc000h -f fffffh 16kb top block 1 0 1 0 x 255 f f8000h -f fffffh 32kb top block 1 0 1 1 0 255 f f8000h -f fffffh 32kb top block 1 1 0 0 1 0 000000h - 000fffh 4kb bottom block 1 1 0 1 0 0 000000h - 001fffh 8kb bottom block 1 1 0 1 1 0 000000h - 003fffh 16kb bottom block 1 1 1 0 x 0 000000h - 007fffh 32kb botto m block 1 1 1 1 0 0 000000h - 007fffh 32kb bottom block free datasheet http://
10 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 10 table1. 1 g d25q128 b protected area size (cmp=1) status register content memory content b p4 bp3 bp2 bp1 bp0 blocks addresses density portion x x 0 0 0 0 to 255 000000h -f fffffh all all 0 0 0 0 1 0 to 251 000000h - fbffffh 16128 kb lower 63/64 0 0 0 1 0 0 to 247 000000h - f7ffffh 15872 kb lower 31/32 0 0 0 1 1 0 to 239 000000h -ef ffffh 15m b lower 15/16 0 0 1 0 0 0 to 223 000000h - df ffffh 14 mb lower 7/8 0 0 1 0 1 0 to 19 1 000000h -bf ffffh 12 mb lower 3/4 0 0 1 1 0 0 to 127 000000h -7 fffffh 8mb lower 1/2 0 1 0 0 1 4 to 255 040000h - ffffffh 16128kb upper 63/64 0 1 0 1 0 8 to 255 080000h - ffffffh 15872kb upper 31/32 0 1 0 1 1 16 to 255 100000h - ffffffh 15mb upper 15/16 0 1 1 0 0 32 to 255 200000h - ffffffh 14mb up per 7/8 0 1 1 0 1 64 to 255 400000h - ffffffh 12mb upper 3/4 0 1 1 1 0 128 to 255 800000h -f fffffh 8mb upper 1/2 x x 1 1 1 none none none none 1 0 0 0 1 0 to 255 000000h -f fefffh 16380 kb l- 4095 / 4096 1 0 0 1 0 0 to 255 000000h - ffdfffh 16376kb l- 2047/2048 1 0 0 1 1 0 to 255 000000h - ffbfffh 16368kb l- 1023/1024 1 0 1 0 x 0 to 255 000000h - ff7fffh 16352kb l- 511/512 1 0 1 1 0 0 to 255 000000h - ff7fffh 16352kb l- 511/512 1 1 0 0 1 0 to 255 001000h - ffffffh 16380kb u- 4095/4096 1 1 0 1 0 0 to 255 002000h - ffffffh 1 6376kb u- 2047 / 2048 1 1 0 1 1 0 to 255 004000h - ffffffh 16368kb u- 1023/1024 1 1 1 0 x 0 to 255 008000h - ffffffh 16352kb u- 511/512 1 1 1 1 0 0 to 255 008000h - ffffffh 16352kb u- 511/512 free datasheet http://
11 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 11 6. s tatus r egister s15 s14 s13 s12 s11 s10 s9 s8 sus cmp rese rved reserved reserved lb qe srp1 s7 s6 s5 s4 s3 s2 s1 s0 srp0 bp4 bp3 bp2 bp1 bp0 wel wip the status and control bits of the status register are as follows: wip bit the write in progress (wip) bit indicates whether the memory is busy in program/eras e/write status register progress. w hen wip bit sets to 1, means the device is busy in program/erase/write status register progress , when wip bit sets 0, means the device is not in program/erase/write status register progress. wel bit the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write status register, program or erase command is accepted. bp4, bp3, b p2, bp1, bp0 bits the block protect (bp4, bp3, bp2, bp1, bp0 ) bits are non - volatile. they define the size of the area to be software protected against program and erase command s. these bits are written with the write status register (wrsr) command . when th e block protect (bp4, bp3, bp2, bp1, bp0) bits are set to 1, the relevant memory area (as defined in table 1). becomes protected against page program (pp) , sector erase (se) and block erase (be) command s. the block protect ( bp4, bp3, bp2, bp1, bp0) bits can be written provided that the hardware protected mode has not been set. the chip erase (ce) command is executed , only if the block protect ( b p2, bp1, bp0) bits are 0. srp1, srp0 bits the status register protect (srp1 and srp0) bits are non - volatile read/write bits in the status register. the srp bits control the method of write protection: software protection, hardware protection, power supply lock - down or one time programmable protection. srp1 srp0 #wp status register description 0 0 x software protec ted the status register can be written to after a write enable command, wel=1.(default) 0 1 0 hardware protected wp # =0, the status register locked and can not be written to. 0 1 1 hardware unprotected wp # =1, the status register is unlocked and can be wr itten to after a write enable command, wel=1. 1 0 x power supply lock - down (1) status register is protected and can not be written to again until the next p ower -d own, p ower -u p cycle. 1 1 x one time program (1) status register is permanently protected and c an not be written to. n ote: 1. when srp1, srp0= (1, 0), a power - down, power - up cycle will change srp1, srp0 to (0, 0) state. free datasheet http://
12 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 12 qe bit the quad enable (qe) bit is a non - volatile read/write bit in the status register that allows quad operation. when the qe bit is set to 0 (default) the wp # pin and hold # pin are enable. when the qe pin is set to 1, the quad io2 and io3 pins are enabled. (the qe bit should never be set to 1 during standard spi or dual spi operation if the wp # or hold # pins are tied directly to the power supply or ground) lb bit the lb bit is non - vola tile one time program (otp) bit in status register (s1 0 ) that provides the write protect control and status to the security registers. the default state of lb is 0, the security registers are unlocked. the lb bit can be set to 1 individually using the write register instruction . the lb bit is one time programmable, once its set to 1, the security registers will become read - only permanently. cmp bit the cmp bit is a non - volatile read/write bit in the status register (s14). it is used in conjunction the bp4 - bp0 bits to provide more flexibility for the array protection. please see the status registers memory protection table for details. the default setting is cmp=0. sus b it the sus bit are read only bit in the status register (s15) that are set to 1 after executing an erase/program suspend (75h) command. the sus bit are cleared to 0 by erase/program resume (7ah) command as well as a power - down, power - up cycle. free datasheet http://
13 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 13 7. commands description all command s, addresses and data are shifted in and out of the device, beginning with the most significant bit o n the first rising edge of s clk after cs# is driven l ow. then, the one - byte command code must be shifted in to the devi ce, most significant bit first on s i, each bit being latched on the rising edges of s clk. see table2, e very command sequence starts with a one - byte command code. depending on the command , this might be followed by address bytes, or by data bytes, or by both or none. cs# must be driven h igh after the last bit of the command sequence has been shifted in. for the command of read, fast read, read status register or release from deep power -d own, and read device id , the shifted - in command sequence is followed by a data - out sequence. cs# can be driven h igh after any bit of the data - out sequence is being shifted out. for the command of page program, sector erase, block erase, chip erase, write status register, write enable, write disable or deep power -d own command , cs# must be driven h igh exactly at a byte boundary, otherwise the command is rejected, and is not executed. that is cs# must driven h igh when the number of clock pulses after cs# being driven l ow is an exact multiple of eight. for page program, if at any time the input byte is not a full byte, nothing will happen and wel will not be reset. table2. command s command name byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 n - bytes write enable 06 h write disable 04 h read status register 05 h (s7 - s0) ( continuous) read status register - 1 35h (s 15 - s 8 ) (continuous) write status register 01 h (s7 - s0) (s 15 - s 8 ) read data 03 h a23 - a16 a15 - a8 a7 - a0 (d7 - d0) (next byte) (continuous) fast read 0b h a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0) (continuous) dual outp ut fast read 3bh a23 -a16 a15 -a8 a7-a0 dummy (d7 - d0) (1) (continuous) dual i/o fast read bbh a23 -a8 (2) a7-a0 m 7 - m0 (2) (d7 - d0) (1) (continuous) quad output fast read 6bh a23 -a16 a15 -a8 a7-a0 dummy (d7 - d0) (3) (continuous) quad i/o fast read ebh a23 -a0 m 7 - m 0 (4) dummy (5) (d7 - d0) (3) (continuous) quad i/o word f ast read (7) e7h a23 -a0 m 7 - m0 (4) dummy (6) (d7 - d0) (3) (continuous) continuous r ead r eset ffh page program 02 h a23 - a16 a15 - a8 a7 - a0 ( d7 - d0 ) next byte quad page program 32h a23 - a16 a15 - a8 a7 - a0 (d7 - d0) (3) sector erase 20 h a23 -a16 a15 -a8 a7-a0 block erase (32k) 52 h a23 - a16 a15 - a8 a7 - a0 block erase (64k) d 8h a23 - a16 a15 - a8 a7 - a0 chip erase c7/60 h program/erase suspend 75h program/erase resume 7ah deep power - d own b9 h release f rom deep power -d own, a nd r ead device id abh dummy dummy dummy (d id7 - d id 0) (continuous) release f rom deep power - d own abh free datasheet http://
14 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 14 read identification 9fh (m id 7- m id 0) (jd id15 - jd id8) (jd id7 - jd id0) (continuous) manufacturer/ device id 90 h dummy dummy 00 h (m7- m0) (id7 - id0) (continuous) manufacturer/ device id by dual i/o 92h a23 -a8 a7- a0, m7-m0 m id 7- m id 0 d id7 - d id0 (continuous) manufacturer/ device id by quad i/o 94h a23 - a0, m7-m0 dummy , m id 7-m id 0 d id7 -d id 0 (continuous) erase security registers (8) 44h a23 -a16 a15 -a8 a7-a0 program security registers (8) 42h a23 -a16 a15 -a8 a7-a0 ( d7 - d0 ) ( d7 - d0 ) read security registers (8) 48h a23 -a16 a15 -a8 a7-a0 dummy ( d7 - d0 ) note: 1. dual output data io0 = (d6, d4, d2, d0) io1 = (d7, d5, d3, d1) 2. dual input address io0 = a22, a20, a18, a16, a14, a12, a 10, a8 a6, a4, a2, a0, m6, m4, m2, m0 io1 = a23, a21, a19, a17, a15, a13, a 11, a9 a7, a5, a3, a1, m7, m5, m3, m1 3. quad output data io0 = (d4, d0, ..) io1 = (d5, d1, ..) io2 = (d6, d2, ..) io3 = (d7, d3,..) 4. quad input address io0 = a20, a16, a12, a8, a4, a0, m4, m0 io1 = a21, a17, a13, a9, a5, a1, m5, m1 io2 = a22, a18, a14, a10, a6, a2, m6, m2 io3 = a23, a19, a15, a11, a7, a3, m7, m3 5. fast read quad i/o data io0 = (x, x, x, x , d4, d0, ) io1 = (x, x, x, x , d 5 , d 1,) io2 = (x, x, x, x , d 6 , d 2,) io3 = (x, x, x, x , d 7 , d 3,) 6 . fast word read quad i/o data io0 = (x, x , d4, d0, ) io1 = (x, x , d5, d1, ) io2 = (x, x , d6, d2, ) io3 = (x, x , d7, d3, ) 7 . fast word re ad quad i/o data: the lowest address bit must be 0. 8. security registers address: free datasheet http://
15 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 15 security register0: a23 - a16=00h, a15 - a8=00h, a7 - a0= byte address; security register1: a23 - a16=00h, a15 - a8= 01 h, a7 - a0= byte address; security register2: a23 - a16=00h, a15 - a8= 02 h, a7 - a0= byte address; security register3: a23 - a16=00h, a15 - a8= 03 h, a7 - a0= byte address. table of id definitions: gd25q 128 b operation code m7-m0 id15 - id8 id7 - id0 9fh c8 40 18 90h c8 17 abh 17 uniform sector dual and quad serial flash GD25Q128b 14 read identification 9fh (m id 7- m id 0) (jd id15 - jd id8) (jd id7 - jd id0) (continuous) manufacturer/ device id 90 h dummy dummy 00 h (m7- m0) (id7 - id0) (continuous) manufacturer/ device id by dual i/o 92h a23 -a8 a7- a0, m7-m0 m id 7- m id 0 d id7 - d id0 (continuous) manufacturer/ device id by quad i/o 94h a23 - a0, m7-m0 dummy , m id 7-m id 0 d id7 -d id 0 (continuous) erase security registers (8) 44h a23 -a16 a15 -a8 a7-a0 program security registers (8) 42h a23 -a16 a15 -a8 a7-a0 ( d7 - d0 ) ( d7 - d0 ) read security registers (8) 48h a23 -a16 a15 -a8 a7-a0 dummy ( d7 - d0 ) note: 1. dual output data io0 = (d6, d4, d2, d0) io1 = (d7, d5, d3, d1) 2. dual input address io0 = a22, a20, a18, a16, a14, a12, a 10, a8 a6, a4, a2, a0, m6, m4, m2, m0 io1 = a23, a21, a19, a17, a15, a13, a 11, a9 a7, a5, a3, a1, m7, m5, m3, m1 3. quad output data io0 = (d4, d0, ..) io1 = (d5, d1, ..) io2 = (d6, d2, ..) io3 = (d7, d3,..) 4. quad input address io0 = a20, a16, a12, a8, a4, a0, m4, m0 io1 = a21, a17, a13, a9, a5, a1, m5, m1 io2 = a22, a18, a14, a10, a6, a2, m6, m2 io3 = a23, a19, a15, a11, a7, a3, m7, m3 5. fast read quad i/o data io0 = (x, x, x, x , d4, d0, ) io1 = (x, x, x, x , d 5 , d 1,) io2 = (x, x, x, x , d 6 , d 2,) io3 = (x, x, x, x , d 7 , d 3,) 6 . fast word read quad i/o data io0 = (x, x , d4, d0, ) io1 = (x, x , d5, d1, ) io2 = (x, x , d6, d2, ) io3 = (x, x , d7, d3, ) 7 . fast word re ad quad i/o data: the lowest address bit must be 0. 8. security registers address: free datasheet http://
16 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 16 7.1. write enable (wren) (06h) the write enable (wren) command is for setting the write enable latch (wel) bit. the write enable latch (wel) bit must be set prior to every page program (pp), sector erase (se), block erase (be), chip erase (ce) and write stat us register (wrsr) command. the w rite enable (wren) command sequence: cs# goes l ow ? sending the write enable command ? cs# goes high. figure 2 . write enable sequence diagram 7.2. write disable (wrdi) (04h) the write disable comman d is for resetting the write enable latch (wel) bit . the write disable command sequence: cs# goes low ? sending the write disable command ? cs# goes high. the wel bit is reset by following condition: power - up and upon completion of the write status register, page program, sector erase, block erase and chip erase commands. figure 3 . write disable sequence diagram 7.3. read status register (rdsr) (05h or 35h) the read status register (rdsr) command is for reading the status register. the status register may be read at any time, even while a program, erase or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new command to the device. it is also possible to read the status register continuously . for command code 05h , the so will output status register bits s7~s0. the command code 35h , the so will output status register bits s15~s8. figure 4 . read status register sequence diagram command 0 1 2 3 4 5 6 7 06 h cs # sclk si so high -z command 0 1 2 3 4 5 6 7 04 h cs # sclk si so high -z command 0 1 2 3 4 5 6 7 05 h or 35 h cs # sclk si so high -z 8 9 10 11 12 13 14 15 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 msb s7~s 0 or s 15 ~s 8 out s7~s 0 or s 15 ~s 8 out msb free datasheet http://
17 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 17 7.4. write status register (wrsr) (01h) the write status register (wrsr) command allows new values to be written to the status register. before it can be accepted, a write enable (wren) command must previously have been executed. after the write enable (wren) command has been decoded and executed, the device sets the write enable latch (wel). the write status register (wrsr) command has no effect on s15 , s1 and s0 of the status register. cs# must be driven h igh after the eighth or sixtee n bit of the data byte has been latched in. if not, the write status register (wrsr) command is not executed. if cs# is driven high after eighth bit of the data byte , the cmp and qe and srp1 bits will be cleared to 0. as soon as cs# is driven h igh, the sel f- timed write status register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write i n progress (wip) bit. the write in progress (wip) bit is 1 during the self - timed write status register cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch (wel) is reset. the write status register (wrsr) command allows the user to change the values of the block protect ( bp4, bp3, bp2, bp1, bp0) bits, to define the size of the area that is to be treated as read - only, as defined in table 1. the write status register (wrsr) command also allows the user to set or reset the status register protect (srp1 and srp 0 ) bit s in accordance with the write protect (wp#) signal. the status register protect (srp1 and srp 0) bit s and write protect (wp#) signal allow the device to be put in the hardware protected mode. the write status register (wrsr) command is not executed once the hardware prot ected mod e is entered. figure 5. write status register sequence diagram 7.5. read data bytes (read) (03h) the read data bytes (read) command is followed by a 3 - byte address (a23 - a0), each bit being latched - in during the rising edge of s clk. then the memory content, at that address, is shifted out on s o, each bit being shifted out, at a max frequency f r , during the falling edge of s clk. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes (read) command . any read data bytes (read) command , while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 6 . read data bytes sequence diagram command 0 1 2 3 4 5 6 7 01 h cs # sclk si so high -z 8 9 10 11 12 13 14 15 msb 7 6 5 4 3 2 1 0 status register in 16 17 18 19 20 21 22 23 15 14 13 12 11 10 9 8 command 0 1 2 3 4 5 6 7 03 h cs # sclk si so high -z 8 9 10 28 29 30 31 32 msb 3 2 1 0 34 35 36 37 33 23 22 21 7 6 5 4 3 2 1 0 38 39 24 - bit address msb data out 1 data out 2 free datasheet http://
18 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 18 7.6. read data bytes at higher speed (fast read) (0bh) the read data bytes at higher speed (f ast r ead ) command is for quickly reading data ou t. i t is followed by a 3 - byte address (a23 - a0) and a dummy byte, each bit being latched - in during the rising edge of s clk. then the memory content, at that address, is shifted out on s o, each bit being shifted out, at a max frequency f c , during the falling edge of s clk. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. figure 7 . read data bytes at higher speed sequence diagram 7.7. dual output fast read (3bh) the dual output fast read command is followed by 3 - byte address (a23 - a0) and a dummy byte, each bit being latched in during the rising edge of sclk, then the memory contents are shifted out 2 - bit per clock cycle from si and so . the command sequence is shown in followed figure8. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. figure 8 . dual outpu t fast read sequence diagram command 0 1 2 3 4 5 6 7 0bh cs # sclk si so high -z 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24 - bit address msb 34 35 36 37 33 6 5 4 3 2 1 0 38 39 data out 1 32 42 43 44 45 41 46 47 40 7 6 5 4 3 2 1 0 7 6 5 7 data out 2 cs # sclk si so msb dummy byte command 0 1 2 3 4 5 6 7 3bh cs # sclk si so high -z 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24 - bit address msb 34 35 36 37 33 5 3 1 7 5 3 1 38 39 data out 1 32 42 43 44 45 41 46 47 40 7 data out 2 cs # sclk si so msb dummy clocks 4 2 0 6 4 2 0 6 6 7 free datasheet http://
19 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 19 7.8. quad output fast read (6bh) the quad output fast read command is followed by 3 - byte address (a23 - a0) and a dummy byte, each bit being latched in during the rising edge of sclk, then the memory contents are shifted out 4 - bit p er clock cycle from io3, io2, io1 and io0. the command sequence is shown in followed figure 9 . the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. figur e 9 . quad output fast read sequence diagram 7.9. dual i / o fast read ( b bh) the dual i/o fast read command is similar to the dual output fast read command but with the capability to input the 3 - byte address (a23- 0) and a continuous read mode byte 2 - bit per clock by si and so, each bit being latched in during the rising edge of sclk, then the memory contents are shifted out 2 - bit per clock cycle from si and so. the command sequence is shown in followed figure 10 . the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. dual i/o fast read with continuous read mode the dual i/o fast read command can further reduce command overhead through setting the continuous read mode bits (m7 - 0) after the input 3 - byte address (a23 -a0). if the continuous read mode bits (m7 - 0) =axh , then the next dual i/o fast read command (after cs# is raised and then lowered) does not require the bbh command code. the command sequence is shown in followed figure11. if the continuous read mode bits (m7 - 0) are any value other than axh, the next command requires the first bbh command code, thus returning to normal operation. a continuous read mode reset command can be used to reset (m7 - 0) before issuing normal command. command 0 1 2 3 4 5 6 7 6bh cs # sclk si( io 0) so( io 1) high -z 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24 - bit address 34 35 36 37 33 1 5 1 5 1 5 1 38 39 byte1 32 42 43 44 45 41 46 47 40 5 dummy clocks 0 4 0 4 0 4 0 4 4 5 wp #( io 2) high -z hold #( io 3) high -z cs # sclk si( io 0) so( io 1) wp #( io 2) hold #( io 3) 2 6 2 6 2 6 2 6 6 3 7 3 7 3 7 3 7 7 byte2 byte3 byte4 free datasheet http://
20 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 20 figure 10 . dual i/o fast read sequence diagram (m7 - 0= 0xh or not axh) figure 11 . dual i/o fast read sequence diagram (m7 - 0= axh) command 0 1 2 3 4 5 6 7 bbh cs # sclk si( io 0) so( io 1) 8 9 10 11 12 13 14 15 6 4 2 0 6 4 2 0 16 17 18 19 20 21 22 23 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 a 23 - 16 a 15 -8 a7-0 m7-0 cs # 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 si( io 0) so( io 1) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 sclk 6 7 byte1 byte2 byte3 byte4 0 1 2 3 4 5 6 7 cs # sclk 8 9 10 11 12 13 14 15 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 a 23 - 16 a 15 -8 a7-0 m7-0 cs # 23 24 25 26 27 28 29 30 31 si( io 0) so( io 1) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 sclk 6 7 byte1 byte2 byte3 byte4 15 16 17 18 19 20 21 22 free datasheet http://
21 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 21 7.10. quad i/o fast read (ebh) the quad i/o fast read command is similar to the dual i/o fast read command but with the capability to input the 3- byte address (a23- 0) and a continuous read mode byte and 4 - dummy clock 4- bit per clock by io0, io1, io3, io4 , e ach bit being latched in during the rising edge of sclk, then the memory contents are shifted out 4- bit per clock cycle from io0, io1, io2, io3 . the command sequence is shown in followed figure1 2 . the first byte addressed can be at any location. the addres s is automatically incremented to the next higher address after each byte of data is shifted out. the quad enable bit (qe) of status register (s9) must be set to enable for the quad i/o fast read command. quad i/o fast read with continuous read mode the quad i/o fast read command can further reduce command overhead through setting the continuous read mode bits (m7 - 0) after the input 3 - byte address (a23 - a0). if the continuous read mode bits (m7 - 0) =axh, then the next quad i/o fast read command (a fter cs# is raised and then lowered) does not require the ebh command code. the command sequence is shown in followed figure13. if the continuous read mode bits (m7 - 0) are any value other than axh, the next command requires the first ebh command code, thus returning to normal operation. a continuous read mode reset command can be used to reset (m7 - 0) before issuing normal command. figure 12 . quad i/o fast read sequence diagram (m7 - 0= 0xh or not axh) figure 13 . quad i/o fast read sequence diagram (m7 - 0= axh) command 0 1 2 3 4 5 6 7 ebh cs # sclk si( io 0) so( io 1) 8 9 10 11 12 13 14 15 4 0 4 0 4 0 4 0 16 17 18 19 20 21 22 23 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 a 23 - 16 a 15 -8 a7-0 m7-0 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 wp #( io 2) hold #( io 3) 4 5 6 7 dummy byte1 byte2 0 1 2 3 4 5 6 7 cs # sclk 8 9 10 11 12 13 14 15 si( io 0) so( io 1) wp #( io 2) hold #( io 3) 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 5 6 7 a 23 - 16 a 15 -8 a7-0 m7-0 dummy byte1 byte2 free datasheet http://
22 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 22 7.11. quad i/o word fast read (e7h) the quad i/o word fast read command is similar to the quad i/o fast read command except that the lowest address bit (a0) must equal 0 and only 2 - dummy clock . the command sequence is shown in followed figure14. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the quad enable bit (qe) of status register (s9) must be set to enable for the quad i/o word fast read command. quad i/o word fast read with continuous read mode the quad i/o word fast read command can further reduce command overhead through setting the continuous read mode bits (m7 - 0) after the input 3 - byte address (a23 - a0). if the continuous read mode bits (m7 - 0) =axh, then the next quad i/o word fast read command (after cs# is raised and then lowered) does not require the e7h command code. the command sequence is shown in followed figure15. if the continuous read mode bits (m7 - 0) are any value other than axh, the next command requires the first e7h command code, thus returning to normal operation. a continuous read mode reset command can be used to reset (m7 - 0) before issuing normal comman d. figure 14 . quad i/o word fast read sequence diagram (m7 - 0= 0xh or not axh) figure 15 . quad i/o word fast read sequence diagram (m7 - 0= axh) command 0 1 2 3 4 5 6 7 e7h cs # sclk si( io 0) so( io 1) 8 9 10 11 12 13 14 15 4 0 4 0 4 0 4 0 16 17 18 19 20 21 22 23 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 a 23 - 16 a 15 -8 a7-0 m7-0 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 wp #( io 2) hold #( io 3) 4 5 6 7 dummy byte1 byte2 4 0 5 1 6 2 7 3 byte3 0 1 2 3 4 5 6 7 cs # sclk 8 9 10 11 12 13 14 15 si( io 0) so( io 1) wp #( io 2) hold #( io 3) 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 5 6 7 a 23 - 16 a 15 -8 a7-0 m7-0 dummy byte1 byte2 4 0 5 1 6 2 7 3 byte3 free datasheet http://
23 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 23 7.12. page program (pp) (02h) the page program (pp) command is f or programm ing t he memory. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit before sending the page program command. the page program (pp) command is entered by driving cs# low, followed by the command code, three address bytes and at least one data byte on s i. if the 8 least significant address bits (a7 - a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (a7 - a0) are all zero). cs# must be driven l ow for the entire duration of the sequence. the page program command sequence: cs# goes low ? sending page program command ? 3- byte address on si ? at least 1 byte data on si ? cs# goes high. the command sequence is shown in figure 16 . if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 25 6 d ata bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. cs# must be driven h igh after the eighth bit of the last data byte has been latched in ; otherwise the page program (pp) command is not executed. as soon as cs# is driven h igh, the self - timed page program cycle (whose duration is t pp ) is initiated. while the page program cycle is in progress, the status register may be read to check the value of the write i n progress (wip) bit. the write in progress (wip) bit is 1 during the self - timed page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a page program (pp) command applied to a page which is protected by the block protect ( bp4, bp3, bp2, bp1, bp0) is not executed. figure 16 . page program sequence diagram command 0 1 2 3 4 5 6 7 02 h cs # sclk si 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24 - bit address 42 43 44 45 41 46 47 40 50 51 52 53 49 54 55 48 6 5 4 3 2 1 0 7 cs # sclk si msb data byte 2 32 33 34 35 7 6 5 4 3 2 1 0 msb 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 data byte 1 data byte 3 data byte 256 msb msb msb 36 37 38 39 2072 2073 2074 2075 2076 2077 2078 2079 free datasheet http://
24 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 24 7.13. quad page program (32h) the quad page program command is for programming the memory using four pins: io0 , io1, io2, and io3 . to use quad page program the quad enable in status register bit9 must be set (qe=1). a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit before sending the page program command. the quad page program command is entered by driving cs# low, followed by the command code (32h) , three address bytes and at least one data byte on io pins. the command sequence is shown in figure 17 . if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 d ata bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. cs# must be driven h igh after the eighth bit of the last data byte has been latched in ; otherwise the quad page program (pp) command is not executed. as soon as cs# is driven h igh, th e self - timed quad page program cycle (whose duration is t pp ) is initiated. while the quad page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self - timed quad page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a quad page program command applied to a page which is protected by the block pro tect ( bp4, bp3, bp2, bp1, bp0) is not executed. figure 17 .quad page program sequence diagram command 0 1 2 3 4 5 6 7 32 h cs # sclk 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24 - bit address 32 33 34 35 4 0 msb 36 37 38 39 si( io 0) so( io 1) wp #( io 2) hold #( io 3) 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 byte1 byte2 cs # sclk si( io 0) so( io 1) wp #( io 2) hold #( io 3) 42 43 44 45 41 46 47 40 50 51 52 53 49 54 55 48 536 537 538 539 540 541 542 543 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 byte 11 4 0 5 1 6 2 7 3 byte 12 4 0 5 1 6 2 7 3 byte253 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 byte256 free datasheet http://
25 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 25 7.14. sector erase (se) (20h) the sector erase (se) command is erased the all data of the chosen sector. a write enable (wren) command must pre viously have been executed to set the write enable latch (wel) bit. the sector erase (se) command is entered by driving cs# l ow, followed by the command code, and 3- address byte on s i. any address inside the s ector is a valid address for the sector erase ( se) command . cs# must be driven l ow for the entire duration of the sequence. the sector erase command sequence: cs# goes low ? sending sector erase command ? 3- byte address on si ? cs# goes high. the command sequence is shown in figure 18 . cs# must be driv en h igh after the eighth bit of the last address byte has been latched in ; otherwise the sector erase (se) command is not executed. as soon as cs# is driven h igh, the self - timed sector erase cycle (whose duration is t se ) is initiated. while the sector erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self - timed sector erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a sector erase (se) command applied to a sector which is protected by the block protect (bp4, bp3, bp2, bp1, bp0) bit (see table 1 .0&1.1 ) is not executed. figure 18 . s ector erase sequence diagram 7.15. 32kb block erase (be) (52h) the 32kb block erase (be) command is erased the all data of the chosen block . a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit. the 32kb block erase (be) command is entered by driving cs# l ow, followed by the command code, and three address bytes on s i . any address inside the b lock is a valid address for the 32kb block erase (be) command . cs# must be driven l ow for the entire duration of the sequ ence. the 32kb block erase command sequence: cs# goes low ? sending 32kb block erase command ? 3- byte address on si ? cs# goes high. the command sequence is shown in figure 19 . cs# must be driven h igh after the eighth bit of the last address byte has been latched in ; otherwise the 32kb block erase (be) command is not executed. as soon as cs# is driven h igh, the self - timed block erase cycle (whose duration is t se ) is initiated. while the block erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self - timed block erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a 32kb block erase (be) command applied to a block which is protected by the block protect ( bp4, bp3, bp2, bp1, bp0) bits (see table 1 .0&1.1 ) is not executed. figure 19 . 32kb block erase sequence diagram command 0 1 2 3 4 5 6 7 20 h cs # sclk si 8 9 29 30 31 msb 2 1 0 24 bits address 23 22 command 0 1 2 3 4 5 6 7 52 h cs # sclk si 8 9 29 30 31 msb 2 1 0 24 bits address 23 22 free datasheet http://
26 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 26 7.16. 64kb block erase (be) ( d8 h) the 64kb block erase (be) command is erased the all data of the chosen block . a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit. the 64kb block erase (be) command is entered by driving cs# l ow, fol lowed by the command code, and three address bytes on s i . any address inside the b lock is a valid address for the 64kb block erase (be) command . cs# must be driven l ow for the entire duration of the sequence. the 64kb block erase command sequence: cs# goes low ? sending 64kb block erase command ? 3- byte address on si ? cs# goes high. the command sequence is shown in figure 20 . cs# must be driven h igh after the eighth bit of the last address byte has been latched in ; otherwise the 64kb block erase (be) command is not executed. as soon as cs# is driven h igh, the self - timed block erase cycle (whose duration is t se ) is initiated. while the block erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self - timed block erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a 64kb block erase (be) command applied to a block w hich is protected by the block protect ( bp4, bp3, bp2, bp1, bp0) bits (see table1 .0&1.1 ) is not executed. figure 20 . 64kb block erase sequence diagram 7.17. chip erase (ce) (60/c7h) the chip erase (ce) command is erased the all data of the chip . a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit . the chip erase (ce) command is entered by driving cs# low, followed by the command code on serial data input ( s i). cs# must be driven low for the entire duration of the sequence. the chip erase command sequence: cs# goes low ? sending chip erase command ? cs# goes high. the command sequence is shown in figure 21 . cs# must be driven h igh after the eighth bit of the command code has been latched in, otherwise the chip erase command is not executed. as soon as cs# is driven h igh, the self - timed chip erase cycle (whose duration is t ce ) is initiated. while the chip erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self - timed chip erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. the chip erase (ce) command is executed only if all block protect (bp2, bp1, bp0) bits are 0. the chip erase (ce) command is ignored if one or more sectors are protected. figure 21 . chip erase sequence diagram command 0 1 2 3 4 5 6 7 d8h cs # sclk si 8 9 29 30 31 msb 2 1 0 24 bits address 23 22 command 0 1 2 3 4 5 6 7 60 h or c 7h cs # sclk si free datasheet http://
27 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 27 7.18. deep power -d own (dp) (b9h) executing the deep power -d own (dp) command is the only way to put the device in the lowest consumption mode (the deep power -d own m ode). it can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all write, program and erase commands. driving cs# h igh deselects the device, and puts the device in the standby m ode (if there is no internal cycle currently in progress). but this mode is not the deep power -d own m ode. the deep power -d own m ode can only be entered by executing the deep power -d own (dp) command. once the device has entered the deep power -d own m ode, all command s are ignored except the release from deep power -d own and read device id (rdi) command . this releases the device from this m ode. the release from deep power -d own and read device id (rdi) command also allows the device id of the device to be output on so. the deep power -d own m ode automatically stops at power -d own, and the device always power -u p in the standby m ode. the deep powe r-d own (dp) command is entered by driving cs# l ow, followed by the command code on s i. cs# must be driven l ow for the entire duration of the sequence. the deep power -d own command sequence: cs# goes low ? sending deep power -d own command ? cs# goes high. the command sequence is shown in figure 22 . cs# must be driven h igh after the eighth bit of the command code has been latched in ; otherwise the deep power -d own (dp) command is not executed. as soon as cs# is driven h igh, it requires a delay of t dp before the s upply current is reduced to i cc2 and the deep power -d own m ode is entered. any deep power -d own (dp) command , while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 22 . deep power -d own sequence diagram 7.19. release from deep power -d own a nd read device id (rdi) (abh) the release from power -d ow n and read device id command is a multi - purpose command . it can be used to release the device fr om the p ower -d own state or obtain the devices electronic identification (id) number. to release the device from the p ower -d own state, the command is issued by driving the cs # pin low, shifting the instruction code abh and driving cs # high as shown in f igure23 . release from p ow er-d own will take t he time duration of t res1 (see ac characteristics) before the device will resume normal operation and other command are accepted. the cs # pin must remain high during the t res1 time duration. when used only to obtain the device id while no t in t he p ower -d own state, the command is initiated by driving the cs # pin low and shifting the instruction c ode abh followed by 3- dummy byte. the device id bits are then shifted out on the falling edge of s clk with most significant bit (msb) first as sh own in f igure 23 . the device id value for the GD25Q128b is listed in manufacturer and device identification table. the device id can be read continuously. the command is completed by driving cs # high. when used to release the device from the p ower -d own stat e and obtain the device id, t he command is the same as previously described, and shown in f igure 23 , except that after cs # is driven high it must remain high for a time duration of t res2 (see ac characteristics). after this time duration the device will res ume normal operation and other command w ill be accepted. if the release from power -d own / device id command is issued while an erase, pr ogram or write cycle is in process (when wip equal 1) the command is ignored and will not have any effects on the curren t cycle. command 0 1 2 3 4 5 6 7 b9h cs # sclk si t dp stand - by mode deep power - down mode free datasheet http://
28 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 28 figure 23 . release power -d own sequence diagram f i gure 24 . release power -d own/ read device id sequence diagram command 0 1 2 3 4 5 6 7 abh cs# sclk si 8 9 29 30 31 msb 2 1 0 3 dummy bytes 23 22 32 33 34 35 36 37 38 7 6 5 4 3 2 1 0 so msb t res2 stand-by mode deep power-down mode high-z device id 7.20. read manufacture id/ device id (rems) (90h) the read manufa cturer/device id command is an alternative to the release from power -d own / device id command that provides both the jedec assigned m anufacturer id and the specific d evice id. the command is initiated by driving the cs# pin low and shifting the command cod e 90 h followed by a 24 - bit address (a23 - a0) of 000000 h . after which, the manufacturer id and the device id are shifted out on the falling edge of s clk with most significant bit (msb) first as shown in figure 25 . if the 24 - bit address is initially set to 000001h, the device id will be read first . figure 25 . read manufacture id/ device id sequence diagram command 0 1 2 3 4 5 6 7 abh cs # sclk si res 1 stand - by mode deep power - down mode t command 0 1 2 3 4 5 6 7 90 h cs # sclk si so high -z 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24 - bit address msb 34 35 36 37 33 6 5 4 3 2 1 0 38 39 32 42 43 44 45 41 46 47 40 7 device id cs # sclk si so msb manufacturer id 6 5 4 3 2 1 0 7 free datasheet http://
29 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 29 7.21. read manufacture id/ device id dual i/o (92h) the read manufacturer/device id dual i/o command is an alternative to the release from power -d own / device id command that provides both the jedec assigned m anufacturer id and the specific d evice id by dual i/o . the command is initiated by driving the cs# pin low and shifting the command code 9 2h followed by a 24 - bit address (a23 - a0) of 000000 h . after which, the manufacturer id and the device id are shifted out on the falling edge of s clk with most significant bit (msb) first as shown in figure 26 . if the 24 - bit address is initially set to 000001h, the device id will be read first . fig ure 26 . read manufacture id/ device id dual i/o sequence diagram 7.22. read manufacture id/ device id quad i/o (94h) the read manufacturer/device id quad i/o command is an alternative to the release from power -d own / device id command th at provides both the jedec assigned m anufacturer id and the specific d evice id by quad i/o . the command is initiated by driving the cs# pin low and shifting the command code 9 4h followed by a 24 - bit address (a23 - a0) of 000000 h . after which, the manufacturer id and the device id are shifted out on the falling edge of s clk with most significant bit (msb) first as shown in figure 27 . if the 24 - bit address is initially set to 000001h, the device id will be read first . command 0 1 2 3 4 5 6 7 92 h cs # sclk si( io 0) so( io 1) 8 9 10 11 12 13 14 15 6 4 2 0 6 4 2 0 16 17 18 19 20 21 22 23 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 a 23 - 16 a 15 -8 a7-0 m7-0 cs # 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 si( io 0) so( io 1) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 sclk mfr id device id 40 41 42 43 6 4 2 0 7 5 3 1 44 45 46 47 6 4 2 0 7 5 3 1 mfr id ( repeat ) device id ( repeat ) mfr id ( repeat ) device id ( repeat ) free datasheet http://
30 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 30 figure 27 . read manufacture id/ device id quad i/o sequence diagram 7.23. read identification (rdid) (9fh) the read identification (rdid) command allows the 8 - bit manufacturer identification to be read, followed by two bytes of device identification. the device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. any read identification (rdid) command while an erase or program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the read identification (rdid) command should not be issued while the device is in deep power -d own m ode. the device is first selected by driving cs# to low. then, the 8 - bit command code for the command is shifted in. this is followed by the 24 - bit device identification, stored in the memory, being shifted out on serial data output, each bit being shifted out during the falling edge of serial clock. the command sequence is shown in figure 28 . the read identification (rdid) command is terminated by driving cs# to high at any time during data output. when c s# is driven h igh, the device is put in the standby m ode. once in the standby m ode, the device waits to be selected, so that it can receive, decode and execute command s. command 0 1 2 3 4 5 6 7 94 h cs # sclk si( io 0) so( io 1) 8 9 10 11 12 13 14 15 4 0 4 0 4 0 4 0 16 17 18 19 20 21 22 23 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 a 23 - 16 a 15 -8 a7-0 m7-0 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 wp #( io 2) hold #( io 3) dummy mfr id did cs # sclk si( io 0) so( io 1) wp #( io 2) hold #( io 3) 24 25 26 27 28 29 30 31 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 mfr id ( repeat ) did ( repeat ) 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 mfr id ( repeat ) did ( repeat ) free datasheet http://
31 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 31 figure 28 . read identification id sequence diagram 7.24. continuous read mode reset (crmr) (ffh) the dual/quad i/o fast read operations , continuous read mode bits (m7 - 0) are implemented to further reduce command overhead. by setting the (m7 - 0) to axh, the next dual /quad i/o fast read operations do not require the bbh/ebh/e7h command code. because the gd25q 128 b has no hardware reset pin, so if continuous read mode bits are set to axh , the GD25Q128 b will not recognize any standard spi commands. so continuous read mode reset command will release the continuous read mode from the axh state and allow standard spi command to be recognized. the command sequence is show in figure2 9. figure 29 . continuous read mode reset sequence diagram 7.25. pro gram/erase suspend (pes) (75h) the erase /program suspend command 75 h, allows the system to interrupt a sector / block erase or page program operation and then read data from any other sector or block. the write status register command (01 h) , page program c ommand (02h), erase/program security registers(44h, 42h) and erase commands (20 h, 52 h, d8 h, c7 h, 60 h) are not allowed during suspend. erase /program suspend is valid only during the sector / block erase or page 0 1 2 3 4 5 6 7 cs # sclk si( io 0) so( io 1) wp #( io 2) hold #( io 3) ffh mode bit reset for quad / dual i /o don ` t care don ` t care don ` t care 0 1 2 3 4 5 6 7 cs # sclk si so 8 9 10 msb 18 19 20 21 17 6 5 4 3 2 1 0 22 23 16 26 27 28 29 25 30 31 24 7 capacity jdid 7- jdid 0 cs # sclk si so msb memory type jdid 15 - jdid 8 6 5 4 3 2 1 0 7 11 12 13 14 15 9 fh 6 5 4 3 2 1 0 7 manufacturer id msb command uniform sector dual and quad serial flash GD25Q128b 31 figure 28 . read identification id sequence diagram 7.24. continuous read mode reset (crmr) (ffh) the dual/quad i/o fast read operations , continuous read mode bits (m7 - 0) are implemented to further reduce command overhead. by setting the (m7 - 0) to axh, the next dual /quad i/o fast read operations do not require the bbh/ebh/e7h command code. because the gd25q 128 b has no hardware reset pin, so if continuous read mode bits are set to axh , the GD25Q128 b will not recognize any standard spi commands. so continuous read mode reset command will release the continuous read mode from the axh state and allow standard spi command to be recognized. the command sequence is show in figure2 9. figure 29 . continuous read mode reset sequence diagram 7.25. pro gram/erase suspend (pes) (75h) the erase /program suspend command 75 h, allows the system to interrupt a sector / block erase or page program operation and then read data from any other sector or block. the write status register command (01 h) , page program c ommand (02h), erase/program security registers(44h, 42h) and erase commands (20 h, 52 h, d8 h, c7 h, 60 h) are not allowed during suspend. erase /program suspend is valid only during the sector / block erase or page 0 1 2 3 4 5 6 7 cs # sclk si( io 0) so( io 1) wp #( io 2) hold #( io 3) ffh mode bit reset for quad / dual i /o don ` t care don ` t care don ` t care 0 1 2 3 4 5 6 7 cs # sclk si so 8 9 10 msb 18 19 20 21 17 6 5 4 3 2 1 0 22 23 16 26 27 28 29 25 30 31 24 7 capacity jdid 7- jdid 0 cs # sclk si so msb memory type jdid 15 - jdid 8 6 5 4 3 2 1 0 7 11 12 13 14 15 9 fh 6 5 4 3 2 1 0 7 manufacturer id msb command free datasheet http://
32 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 32 program operation. a m aximum of time of tsus ( see ac characteristics) is required to suspend the program/erase operation. while the erase/program suspend cycle is in progress, the read status register command may still be accessed for checking the status of the wip bit or sus bit . the wip bit or sus bit are a 1 during the erase/program suspend cycle and becomes a 0 when the cycle is finished and the device is ready to accept read command. a power - off during the suspend period will reset the device and release the suspend state. the command sequence i s show in figure30. figure 30 . program/erase suspend sequence diagram 7.26. program/erase resume (per) (7ah) the program/erase resume command must be written to resume the sector/block erase or program operation after a program/eras e suspend command. after issued the wip bit or sus bit in the status register will be set to 1 and the sector/block erase or program operation will completed. the program/erase resume command will be ignored unless a program/erase suspend is active. the co mmand sequence is show in figure31. figure 31 . program/erase resume sequence diagram 7.27. erase security registers (44h) the gd25q 128 b provides three 256 - byte security registers which can be erased and programmed individually. th ese registers may be used by the system manufacturers to store security and other important information separately from the main memory array. the erase security registers command is similar to sector/block erase command. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit. the erase security registers command sequence: cs# goes low ? sending erase security registers command ? cs# goes high. the command sequence is shown in figure 32 . cs# must be dri ven h igh after the eighth bit of the command code has been latched in, otherwise the erase security registers command is not executed. as soon as cs# is driven h igh, the self - timed erase security registers cycle (whose duration is t se ) is initiated. while the erase security registers cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self - timed erase security registers cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. the security registers lock bit (lb) in the status register can be used to otp protect the security registers. once the lb bit is set to 1, the security command 0 1 2 3 4 5 6 7 75 h cs # sclk si so high -z tsus accept read command command 0 1 2 3 4 5 6 7 7ah cs # sclk si so resume erase / program free datasheet http://
33 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 33 registers will be permanently locked; the erase security registers command will be ignored. address a23 - a16 a15 - a10 a9 - a0 security registers 00000000 000000 don t care figure 32 . erase security registers command sequence diagra m 7.28. program security registers (42h) the program security registers command is similar to the page program command. it allows from 1 to 256 bytes security registers data to be programmed. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit before sending the program security registers command. the program security registers command is entered by driving cs# low, followed by the command code (42h) , three address bytes and at least one data byte on s i. as soon as cs# is driven h igh, the self - timed program security registers cycle (whose duration is t pp ) is initiated. while the program security registers cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self - timed program security registers cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. if the security regi sters lock bit (lb) is set to 1, the security registers will be permanently locked. program security registers command will be ignored. address a23 - a16 a15 - a8 a7 - a0 security registers 0 00h 00h byte address security registers 1 00h 01h byte address secu rity registers 2 00h 02h byte address security registers 3 00h 03h byte address figure 33 . program security registers command sequence diagram command 0 1 2 3 4 5 6 7 44 h cs # sclk si 8 9 29 30 31 msb 2 1 0 24 bits address 23 22 command 0 1 2 3 4 5 6 7 42 h cs # sclk si 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24 - bit address 42 43 44 45 41 46 47 40 50 51 52 53 49 54 55 48 6 5 4 3 2 1 0 7 cs # sclk si msb data byte 2 32 33 34 35 7 6 5 4 3 2 1 0 msb 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 data byte 1 data byte 3 data byte 256 msb msb msb 36 37 38 39 2072 2073 2074 2075 2076 2077 2078 2079 free datasheet http://
34 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 34 7.29. read security registers (4 8 h) the read security registers command is similar to fast read command. the command i is followed by a 3 - byte address (a23 - a0) and a dummy byte, each bit being latched - in during the rising edge of s clk. then the memory content, at that address, is shifted out on s o, each bit being shifted out, at a max frequency f c , during the falling edge of s clk. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. once the a9-a0 address reaches the last byte of the register (byte 3 ffh), it will reset to 000h, the command is completed by driving cs# high. address a23 - a16 a15 - a10 a9 - a0 security registers 0 00000000 000000 address figure 34 . read security registers command sequence diagram command 0 1 2 3 4 5 6 7 48 h cs # sclk si so high -z 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24 - bit address msb 34 35 36 37 33 6 5 4 3 2 1 0 38 39 data out 1 32 42 43 44 45 41 46 47 40 7 6 5 4 3 2 1 0 7 6 5 7 data out 2 cs # sclk si so msb dummy byte free datasheet http://
35 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 35 8. electrical characteristics 8.1. power - on timing table 3. power - up timing and write inhibit threshold symbol parameter min max unit tvsl vcc(min) t o cs# low 10 us tpuw time delay before write i nstruction 1 10 ms vwi write inhibit voltage 1 2.5 v 8.2. initial delivery state the device is delivered with the memory array erased: all bits are set to 1(each byte contains ffh).the status register contains 00h (all status register bits are 0). 8.3. data retention and endurance parameter te st condition min units minimum pattern data retention time 150 ? 10 years 125 ? 20 years erase/program endurance - 40 to 85 ? 100k cycles 8.4. latch up characteristics parameter min max input voltage r espect t o vss o n i/o p ins - 1.0v v cc+1.0v vcc current - 100ma 100ma vcc(max) vcc(min) v wi reset state tpuw tvsl chip selection is not allowed program , erase and write command are ignored read command is allowed device is fully accessible time free datasheet http://
36 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 36 8.5. absolute maximum rating s parameter value unit ambient operating temperature - 40 to 85 ? storage temperature -6 5 to 1 50 ? output short circuit current 200 ma applied input/output voltage - 0.5 to 4.0 v vcc - 0.5 to 4.0 v 8.6. capacitance measurement conditions symbol parameter min ty p max unit conditions cin input capacitance 6 pf vin=0v cout output capacitance 8 pf vout=0v c l load capacitance 30 pf input rise a nd fall time 5 ns input p ul se voltage 0.2vcc to 0.8vcc v input t iming r efer ence voltage 0.3vcc to 0.7vcc v output t iming r eference voltage 0.5vcc v figure 35 . input test waveform and measurement level vss 20ns maximum negative overshoot waveform maximum positive overshoot waveform 20ns 20ns vss -2.0v vcc 20ns 20ns 20ns vcc + 2.0v 0.8vcc 0.2vcc 0.7vcc 0.3vcc 0.5vcc ac measurement level input timing reference level output timing reference level note: input pulse rise and fall time are <5 ns free datasheet http://
37 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 37 8.7. dc characteristic (t= - 40 ? ~85 ? , vcc=2.7~3.6v) symbol parameter test condition min. typ max. unit. i li input leakage current 2 ?? i lo output leakage current 2 ?? i cc1 standby current cs#=vcc, v in =vcc or vss 30 ?? i cc2 deep power -d own current cs#=vcc, v in =vcc or vss 1 5 ?? i cc3 operating current (read) clk=0.1vcc / 0.9vcc at 104mhz, q=open (*1 i/o) 15 20 ma clk=0.1vcc / 0.9vcc at 80 mhz, q=open (*1,*2,*4 i/o) 13 18 ma i cc4 operating current (pp) cs#=vcc 10 ma i cc5 operating current(wrsr) cs#=vcc 10 ma i c c6 operating current (se) cs#=vcc 10 ma i cc7 operating current (be) cs#=vcc 10 ma v il input low voltage - 0.5 0.2vcc v v ih input high voltage 0.7vcc vcc+0.4 v v ol output low voltage i ol =1.6ma 0.4 v v oh output high voltage i oh =- ????? vcc - 0.2 v free datasheet http://
38 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 38 8.8. ac characteristics (t= - 40 ? ~85 ? , vcc=2.7~3.6v, c l =3 0pf) symbol parameter min. typ. max. unit. f c serial clock frequency f or: all command except for 03h dc. 104 mhz f r serial clock frequency f or: read (03h) dc. 80 mhz t clh seri al clock high time 4 .5 ns t cll serial clock low time 4 .5 ns t clch serial clock rise time (slew rate) 0. 2 v/ns t chcl serial clock fall time (slew rate) 0. 2 v/ns t slch cs# active setup time 5 ns t chsh cs# active hold time 5 ns t shch cs# not active setup time 5 ns t chsl cs# not active hold time 5 ns t shsl cs# high time ( read/write ) 20 ns t shqz output disable time 6 ns t clqx output hold time 0 ns t dvch data in setup time 2 ns t chdx data in hold time 2 ns t hlch hold# low setup time (relative to clock) 5 ns t hhch hold# high setup time (relative to clock) 5 ns t chhl hold# high hold time (relative to clock) 5 ns t chhh hold# low hold time (relative to clock) 5 ns t hlqz hold# low t o high - z output 6 ns t hhq x hold# l ow t o low - z output 6 ns t clqv clock low to output valid 7 ns t whsl write protect setup time b efore cs# low 20 ns t shwl write protect hold time a fter cs# high 100 ns t dp cs# high t o deep power -d own mode 0.1 ?? t res1 cs# high t o standby mode w ithout electronic signature r ead 5 ?? t res 2 cs# high t o standby mode w ith electronic signature r ead 5 ?? t s us cs# high to next command after suspend 2 us t w write status register cycle time 2 15 ms t pp page programming time 0. 4 2.4 ms t se sector erase time 10 0 3 00/600(1) ms t be 1 block erase time (32k bytes ) 2 00 400 / 800(2) ms t be 2 block erase time (64k bytes) 4 00 600 /1 000(3) ms t ce chip erase time (GD25Q128 b) 60 120 s note: 1. max value tsewith<50k cycles is 300ms and >50k & <100k cycles is 6 00ms. free datasheet http://
39 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 39 2. max value tbe1with<50k cycles is 4 00ms and >50k & <100k cycles is 8 00ms. 3. max value tbe2with<50k cycles is 600ms and >50k & <100k cycles is 10 00ms. figure 36 . serial input timin g figure 37 . output timing figure 38 . hold timing sclk cs # si msb so high -z lsb tchsl tslch tdvch tchdx tshch tchsh tchcl tclch tshsl cs # sclk so si least significant address bit ( lib ) in tclqv tclqx tclqx tclqv tch tcl tshqz lsb tqhql tqlqh cs # sclk so hold # tchhl thlqz thlch tchhh thhch thhqx si do not care during hold operation . free datasheet http://
40 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 40 9. ordering information note: 1. standard bulk shipment is in tube. any alternation of packing method (for tape, r e el and tray etc.), please advi se in advance. gd xx x xx x x x x x green code temperature range i: industrial (-40 ? to +85 ? ) package type density series q:3v,4 kb sector , quad i /o product family 25: serial flash 128:128m- bit f : sop 16 300 mil packing type t or no mark : tube y: tray r:tape & reel y : wson 8 (8*6 mm ) g: pb free & halogen free green package generation b : b version z : tfbga 24 free datasheet http://
41 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 41 10. package information 10.1. package sop 16 3 00mil dimensions symbol a a1 a2 b c d e e1 e l l1 s ? unit mm min 2.36 0.10 2.24 0.36 0.20 10.10 10.10 7.42 0.40 1.31 0.51 0 nom 2.55 0.20 2.34 0.41 0.2 5 10.30 10.35 7.52 1.27 0.84 1.4 4 0.64 5 max 2.75 0.30 2.44 0.51 0.30 10.50 10.60 7.60 1.27 1.57 0.77 8 inch min 0.093 0.00 4 0.088 0.014 0.00 8 0.397 0.397 0.292 0.016 0.052 0.02 0 0 nom 0.100 0.00 8 0.092 0.016 0.010 0.405 0.407 0.296 0.050 0.033 0.05 7 0.02 5 5 max 0.108 0.01 2 0.096 0.020 0.01 2 0.413 0.417 0.299 0.050 0.062 0.03 0 8 note:both package length and width do not include mold flash. 1 8 9 15 e1 e d a a2 a1 s e b l l1 c ? free datasheet http://
42 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 42 10.2. package wson8 (8*6mm) dimensions symbol a a1 a2 b d d1 e e1 e k l unit mm min 0.70 0.35 7.90 3.25 5.90 4.15 0.55 nom 0.75 0.20 0.40 8.00 3.42 6.00 4.22 1.27 1.80 0.60 max 0.80 0.05 0.45 8.10 3.50 6.10 4.40 0.6 5 inch min 0.028 0.014 0.311 0.128 0.232 0.163 0.022 nom 0.030 0.008 0.016 0.315 0.135 0.236 0.166 0.050 0.071 0.024 max 0.032 0.002 0.019 0.319 0.138 0.240 0.173 0.027 note:both package length and width do not include mold flash. d e top view d1 e1 b e bottom view l k 1 a2 a1 a side view free datasheet http://
43 r ev.1. 1 GD25Q128bxigx uniform sector dual and quad serial flash 4 3 - uniform sector dual and quad serial flash GD25Q128b 43 10.3. package tf bga - 24ball (6*4 ball array) dimensions symbol a a1 a2 b d d1 e e1 e unit mm min 0.25 0.35 5.90 7.90 nom 0.30 0.85 0.40 6.00 3.00 8.00 5.00 1.00 max 1.20 0.35 0.45 6.10 8.10 inch min 0.010 0.014 0.232 0.311 nom 0.012 0.033 0.016 0.236 0.120 0.315 0.200 0.039 max 0.047 0.014 0.018 0.240 0.319 note:both package length and width do not include mold flash. seating plane a b c d e f 4 3 2 1 a b c d e f 1 2 3 4 e d e1 e e d1 ? b a2 a1 c 0. 10 c 0. 10 c a free datasheet http://

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